1. Technical Field
The embodiments described herein relate to a semiconductor memory device and, more particularly, to a phase-change memory device and a method for manufacturing the same.
2. Related Art
A phase change random access memory (PRAM) is regarded as a non-volatile memory device. PRAMs are manufactured using a phase-change material which is capable of reversibly changing phases between an ordered crystalline solid state phase and a disordered amorphous solid state phase as a function of temperature. PRAMs also provide a way of storing a set status or a reset status because their different solid state phases exhibit distinctly different resistance difference.
PRAM memory devices can be designed to be highly integrated. As a result, word line resistances in highly integrated PRAMs increase. Recently, metal contacts can be configured to be arranged between the cell strings and metal word lines so that they are connected to the metal contacts which minimizes this problem of an increased resistance of the word line.
FIG. 1 is a sectional view of a conventional PRAM. Referring to FIG. 1, diodes 107 are formed on a semiconductor substrate 101 which a junction region 103 as a word line is formed therein. Phase change material patterns 109 are formed on the diodes 107 to form respective unit memory cells. Top electrode contacts 113 and bit lines 117 are formed on the phase change material patterns 109. Herein, the reference numerals 105, 115 and 119 designate a first though a third interlayer insulating layers, respectively.
Word line contacts 121 are arranged to be coupled to the junction region 103 between adjacent cell strings 125 along every predetermined number of cell strings 125. A metal word line 123 which is electrically connected, i.e., coupled, to the word line contacts 121 are arranged vertically relative to the bit lines 117.
Typically, the word line contacts 121 are arranged every 8 unit memory cells. However, as the integration of a semiconductor memory device increases, the diameter of the word line contact 121 decreases. Accordingly, it is difficult to ensure the desired CD (Critical Dimension) in patterning holes for the word line contacts 121. Furthermore, since the space between the patterns becomes narrower, then a bridge with the adjacent holes can occur and thereby reduces the yield of the device.
FIG. 2 is a stylized lay out of the PRAM in FIG. 1. Referring to FIG. 2, the word line contacts 121 are shown arranged between every eight units of memory cells in the extension direction of the metal word line 123.
As the level of integration increases for semiconductor memory devices, it is becoming more difficult to ensure the desired CD. Also, as the distance D1 between the adjacent word line contacts 121 increases, unwanted bridges can occur between adjacent word line contacts 121. Furthermore, misalignment is also more likely to occur in forming the word line contacts 121. Furthermore, it becomes more and more difficult to ensure the minimum requirements to prevent misalignments as a result of downsizing the dimensional layout ratios of the device.
Furthermore, the process of forming contact holes with the two-layered through four-layered stack structures is carried out so as to form the word line contact 121. Since the photo and exposure process for the contact hole is carried out by using the high-cost apparatus, the cost required to form the word line contacts 121 in these types of stack structures which are arranged every 8 cell strings increases. Furthermore, when the diameter in the contact hole is reduced based on the demands for more highly integrated devices, then gap filling is more likely to be degraded which reduces the productivity of device.